Tuning adaptive microarchitectures

A program’s microarchitectural resource requirements change as it goes through different phases of execution. Microprocessors, on the other hand, are designed to provide a fixed set of resources – leading to sub-optimal power and/or performance. Multi-configuration hardware that adapts to the programs’ requirements has been shown to provide a much better power/performance tradeoff. In this paper, we describe an adaptive microarchitecture that employs several multi-configuration units – instruction cache, data cache, L2 cache and branch predictor. We present a profiling architecture and unified tuning algorithms to manage these units. The algorithms detect program phase changes and use a novel technique to decouple the tuning of each unit. The paper also addresses several important issues associated with program phase detection such as correlation of instruction and data working set changes, phase stability and optimal working set sampling rates. We show that working set signatures generated by sampling as low as one instruction and one data reference every eight instructions provides sufficient information to accurately detect working set changes and estimate working set sizes. Detailed simulations show that tuning algorithms based on these signatures can achieve up to 45% reduction in instruction cache size, 20% reduction in data cache size, 26% reduction in L2 cache size and 29% reduction in branch predictor size for a performance reduction of less than 1%.